1. Technical Field
The disclosure relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus using a data mask method.
2. Related Art
A typical data mask operation may be performed so as not to change information which has been written in a specific memory area even though new data is written in a semiconductor memory apparatus. In particular, when data having the same information are inputted and outputted, the data mask operation may prevent unnecessary input and output of the corresponding data.
In a typical semiconductor memory apparatus such as a DRAM, the data mask operation may be performed according to the following process. In a DRAM, a write operation is performed in a manner that a pair of segment input/output lines SIO/SIOB are precharged according to inputted data and a pair of bit lines BL/BLB amplified by a bit line sense amplifier are electrically coupled to the pair of segment input/output lines SIO/SIOB while a column control signal YI is activated. In the data mask operation, the pair of segment input/output lines SIO/SIOB are precharged to a predetermined level, for example, a core voltage VCORE without using the inputted data, and the pair of bit lines BL/BLB and the pair of segment input/output lines SIO/SIOB precharged to the core voltage VCORE are electrically coupled respectively while the column control signal YI is activated in case of a data write operation. Thus, the logic values of the pair of bit lines BL/BLB are not changed.
In such a data mask operation, when the pair of bit lines BL/BLB amplified by the bit line sense amplifier and the pair of segment input/output lines SIO/SIOB precharged to the core voltage VCORE are electrically coupled in response to the column control signal YI, charge sharing occurs between the pair of bit lines BL/BLB and the pair of segment input/output lines SIO/SIOB respectively. For example, since the pair of bit lines BL/BLB were amplified to the levels of an external voltage VDD and a ground voltage VSS, respectively, and the pair of segment input/output lines SIO/SIOB are precharged to the level of the core voltage VCORE, a temporary voltage rise/drop occurs in the pair of bit lines BL/BLB while the column control signal YI is activated. The bit line sense amplifier is designed in such a manner that an unexpected change in the logic values of the pair of bit lines BL/BLB does not occur even though such a temporary voltage rise/drop occurs.
The column control signal YI is a signal for controlling the operation of electrically coupling the pair of bit lines BL/BLB to the pair of segment input/output lines SIO/SIOB in a read/write operation, and may be generated by decoding a column address signal while a strobe signal is activated. Therefore, the strobe signal becomes a source signal of the column control signal YI. Furthermore, the column control signal YI is set to be activated with a longer pulse width during a write operation than during a read operation, in order to stably write data.
One problem with a conventional semiconductor memory apparatus is that undesired data may be written during the data mask operation. With a high-integration and low-power trend of a semiconductor memory apparatus, the drivability of a bit line sense amplifier has been gradually reduced. Accordingly, an unexpected logic value transition may occur in the pair of bit lines BL/BLB. More specifically, as described above, a temporary voltage rise/drop may occur in the pair of bit lines BL/BLB due to the charge sharing between the pair of bit lines BL/BLB and the pair of segment input/output lines SIO/SIOB precharged to the core voltage VCORE during the period in which the column control signal YI is activated in case of a data mask operation. In a normal data mask operation, the bit line sense amplifier should be able to tolerate such a temporary voltage rise/drop at this time. However, as the drivability of the bit line sense amplifier is reduced, the bit line sense amplifier may not tolerate such a temporary voltage rise/drop, but may change the logic values of the pair of bit lines BL/BLB.